9.5 A CMOS circuit is shown is Fig. P9.5. Suppose that the precharge transistor was chosen...

9.5 A CMOS circuit is shown is Fig. P9.5. Suppose that the precharge transistor was chosen such that the node X is guaranteed to be charged to V_DD. All nMOS transistors have W/L = 20. Determine how long it takes for the node voltage at X to decrease to 0.8 V_DD after the clock signal pulse goes to high (with zero rise time) when input voltages at A,B,D are 5 V and the input voltage at C is zero. Assume the following parameter values:

• γ = 0.0 V^1/2

• V_T0 = 1.0V

• k′_n = 10μA/V²

Hint: The NMOS transistor tree between the node X and the ground can be approximated by an equivalent transistor with an effective W/L.

Figure P9.5