Question

could use some help with this. please show work so that i can understand how its done as well.

1. A BCD-to-seven-segment decoder is a combinational circuit that converts a decimal digit in BCD to an appropriate code for the selection of segments in an indicator used to display the decimal digit in a familiar form. The seven outputs of the decoder (a, b, c, d, e, f, g) select the corresponding segments in the display. Using a truth table and Karnaugh maps, design the BCD-to-seven-segment decoder using a minimum number of gates. The six invalid combinations should result in a blank display. Determine the total number of gate inputs that will be needed to implement the decoder. (20 points)

Answer 1

According to the question there are four inputs (let say W, X, Y, Z) and 7 outputs (A, B, C, D, E, F, G), these 7 outputs are the segments of the decoder, the arrangement of these 7 segments are as follows:-

  

C A G E B D

The truth table of BCD-to seven segment decoder is as follows:-

W	X	Y	Z	A	B	C	D	E	F	G
0	0	0	0	1	1	1	1	1	1	0
0	0	0	1	1	1	0	0	0	0	0
0	0	1	0	1	0	1	1	1	0	1
0	0	1	1	1	1	1	1	0	0	1
0	1	0	0	1	1	0	0	0	1	1
0	1	0	1	0	1	1	1	0	1	1
0	1	1	0	0	1	1	1	1	1	1
0	1	1	1	1	1	1	0	0	0	0
1	0	0	0	1	1	1	1	1	1	1
1	0	0	1	1	1	1	1	0	1	1
1	0	1	0	X	X	X	X	X	X	X
1	0	1	1	X	X	X	X	X	X	X
1	1	0	0	X	X	X	X	X	X	X
1	1	0	1	X	X	X	X	X	X	X
1	1	1	0	X	X	X	X	X	X	X
1	1	1	1	X	X	X	X	X	X	X

Since BCD values are only valid from 0 to 9 therefore for the rest combinations (10-15) the value of 7 segment decoder will be blank, since blank do not have any fixed value therefore we used (don't care).

Using above truth table the equations for each output segment using K-map is derived as follows:-

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42 ww ool vo 3 -- =ñž + y z E 0 1 ५ SI 7 To 11 X 3 X 5 X 4 X. To no 9 jo 42 01 o 0 7 3 2. 5 7 G 1 X F = y + xy + x3 + W 13 X is y X 1 10 8 9 10 42 wa ol 11 06 0 3 2 7 ol G = wt tyt i X t ng + x 4 12 X, 13 X is in X о - 1 8 11 X

Using above equations the circuit diagram of the BCD- seven segment decoder is as follows:-

From the above equations the number of input gates required are as follows:-

9 N. 3 q * . A B С D D E . D G ET

Segment	AND gate	OR gate
A	2	2
B	0	2
C	2	3
D	5	4
E	2	1
F	3	3
G	3	3

These are the maximum number of input gates (total 17 AND, 18 OR) that can be used in designing the above circuit, but this can be minimized by using the same circuit for common product terms.