Question

4. Given the following Processor Datapath Latencies, Determine the addi instruction latency. List the delay components of this instruction's latency using the schematic shown in Fig 1 below Add Sum Shift Branch MemRead MertoReg Instruction (6-0 - Control ALUOD Mem Winte ALUST RegWrite Instruction (19-15] Read Instruction (24-20 Zero Read register 1 Read Read data 1 register 2 Write Road register data 2 Write data Registers Instruction (31-01 Instruction memory ALU ALUL Instruction (11-7) Address data result White Data data memory Instruction (31-0 imm Gen ALU control Instruction (30.14-12

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Answer 1

We'll start with the Arithmetic and Logic Unit (the ALU). This unit implements arithmetic and logic operations, as the name suggests:

addition, subtraction, multiplication, and division;

and, or, not, nor, and xor;

comparison;

shifting.

In addition to the main ALU, there are three "mini-ALUs": one to add 4 to the program counter, another to compute a branch address, and the third to shift the contents of a branch immediate field.

The adder

The adder is given two 32-bit integers as inputs, and produces the sum as output.

You have already seen how one might go about designing an adder. Here's a quick review. Examining the truth table seems fruitless—there are 264 rows! Instead, we look for a way to break the problem down into smaller circuits that can be combined into the circuit we want. The standard addition-by-hand algorithm we learned in grade school provides a hint for how to do this.

Consider, for example, the addition of two 4-bit values a and b, producing a sum s.

a3 + a2 + a1 + a0

+ b3 + b2 + b1 + b0

------------------------

s3 + s2 + s1 + s0

We start by adding the least significant bits, computing a0 + b0 = s0. A second output will represent a potential carry into column 1; we'll call that c1. Here's the truth table.

a0 b0 s0 c1

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Adding in the second column from the right requires slightly different behavior, namely the use of an extra input—the carry from the first column. Here's its truth table.

  

a1 b1 c1 s1 c2

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Constructing a 32-bit adder out of 1-bit adders

One may observe that the 1-bit adder just designed for the second addition column works for the remaining columns as well. That is, the same structure can be used to produce sk and ck+1 from ak, bk, and ck, for k ranging from 1 to 31. The resulting circuit is diagrammed below.

In fact, the addition in the rightmost column need not be treated as a special case. The adders used for columns 1-31 can also be used in column 0, merely by providing an input of 0 as the carry-in.

This circuit is called a ripple adder, since carries "ripple" from the rightmost to the leftmost columns. The possibility of a rippling carry constrains the speed of the adder. P&H section B.6 describes an adder design that trades simplicity for speed.

One of the very important properties of this adder is that it works for unsigned numbers and signed numbers (2's complement). In fact, it doesn't even need to know which kind it is working on—it does just the same thing in either case. Addition is moving clockwise on the number wheel. Plug in a positive and a negative 4-bit number in the 4-bit adder that you built last week. Convince yourself it does the right thing.

Overflow

It is very useful to have the adder signal overflow when it occurs. This is one place where signed and unsigned arithmetic differs.

In adding unsigned values, detecting overflow is pretty obvious. If there is a carry out from the MSB there was an overflow. This is where you cross from FF...F to 00...0 on the number wheel.

The more interesting case is detecting overflow in addition of signed integers. If you add a positive and a negative number there cannot possibly be an overflow because the magnitude of A–B (for positive A and B) must be less than the larger of A and B.

When you add two positive signed values and an overflow occurs, there is no carry out. What happens instead?

Whenever you add two negative numbers there is a carry out since both have the sign bit on, so that is not what tells you there is an overflow. What does?

If you remember the number wheel, an overflow occurs when the result of the arithmetic operation crosses from the most positive numbers to the most negative, or vice versa. In other words, overflow occurs when adding two positive numbers produces a negative sum, or vice versa.

It is possible to detect the overflow using only the inputs and outputs of the most significant bit slice of your adder. Write down the truth table for the FA that forms the MSB of your adder. Add a 6th column that is overflow. Derive a boolean expression for the overflow. Can you reduce this to a single gate? Add this simple overflow detector to your 4-bit adder.