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In this exercise we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word: 10101100011000100000000000010100. Assume tha

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Answer #1

Solution:

4.7 .1)

The instruction word is

\(\begin{array}{lllll}1010 & 1100 & 0110 & 0010 & 0000\end{array}\)

0100

Sign extend:

The instruction takes least significant 16 bit and extends to 32 bit.

Lowest 16 bits are

0000000000010100

Extend it to 32 bits

\(\begin{array}{llllllll}0000 & 0000 & 0000 & 0000 & 0000 & 0000 & 0001 & 0100\end{array}\)

Shift left 2

The instruction takes the least significant 26 bits and expands by it to 28 bits by shifting two values.

The lower 26 bits of the instruction is

00011000100000000000010100

Expand to 28 bits by shift left 2

$$ \begin{array}{|l|llllllll|} \hline \text { Sign extend } & 0000 & 0000 & 0000 & 0000 & 0000 & 0000 & 0001 & 0100 \\ \hline \text { Shift left 2 } & 0001 & 1000 & 1000 & 0000 & 0000 & 0101 & 0000 & \\ \hline \end{array} $$

4.7 .2)

ALUOp :

ALUOp is the least significant 2 bits.

The least significant 2 bits of the instruction is 00


Instruction:

Instructions is the least significant 6 bits

The least significant 6 bits of the instruction is

010100

$$ \begin{array}{|l|l|} \hline \text { ALUOp } & 00 \\ \hline \text { Instruction } & 010100 \\ \hline \end{array} $$

4.7 .3)

The new \(\mathrm{PC}\) address is

\(\mathrm{PC}=\mathrm{PC}+4\)

Path:

From \(\mathrm{PC}\) to \(\mathrm{Add}(\mathrm{PC}+4)\) that add 4 to the \(\mathrm{PC}\) value which branch to \(\mathrm{MUX}\), after that jump to MUX and then to \(\mathrm{PC}\).

\(4.7 .4)\)

Write Register MUX:

2 Or 0 , since write registers are not used. Here the value is stored to memory.

ALU MUX:

Immediate register is used. The sign extend is \(\begin{array}{llllllll}0000 & 0000 & 0000 & 0000 & 0000 & 0000 & 0001 & 0100\end{array}\)

So the ALU MUX value is 20

Branch and Jump MUX:

Used for incrementing the \(\mathrm{PC}\) addresses. So they have value \(\mathrm{PC}+4\)

ALU/Mem MUX:

since write registers are not used, it have don't care values \(\mathrm{X}\).

$$ \begin{array}{|l|l|l|l|l|} \hline \text { WriteRegisterMux } & \begin{array}{l} \text { ALU/Mem } \\ \text { Mux } \end{array} & \text { Branch Mux } & \text { Jump Mux } & \text { ALU Mux } \\ \hline 2 \text { or } 0 & \mathrm{X} & \mathrm{PC}+4 & \mathrm{PC}+4 & 20 \\ \hline \end{array} $$


4.7 .5)

ALU Unit:

For ALU one of the input is read the first register which is 0011 (3) and register 3 has value -3 and the other input is extended 16 bit sign bit that is \(20 .\)

Add (Branch Unit):

One input is \(\mathrm{PC}+4\) and the other input is 16 bit extended sign bit that is 20 shifted left \(2,\) so the value is \(20^{*} 4=80\).

Add \((P C):\)

One of the inputs is \(\mathrm{PC}\) and other input is 4

$$ \begin{array}{|l|l|l|} \hline \text { ALU Unit: } & \text { Add (Branch Unit): } & \text { Add (PC): } \\ \hline-3 \text { and } 20 & \text { PC+4 and } 80 & \text { PC and } 4 \\ \hline \end{array} $$

4.7 .6)

Read Register 1 :

Bit number \(25-21: 0011 \rightarrow 3\)

Read Register 2 :

Bit number \(20-16: 0010 \rightarrow 2\)

Write Register and Write Data:

since the instruction is store, there is no register write operation. so they have don't care values

RegWrite:

No register write operation. So the value is 0

$$ \begin{array}{|l|l|l|l|l|} \hline \text { Read Register } \mathbf{l} & \text { Read Register 2 } & \text { Write Data } & \begin{array}{l} \text { Write } \\ \text { Register } \end{array} & \text { RegWrite } \\ \hline 3 & 2 & \mathrm{X} & \mathrm{X}(2 \text { or } 0) & 0 \\ \hline \end{array} $$


answered by: HAOnline
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