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Q4. (20 points) Consider the following sequence of instructions being processed on the 5-stage RISC-V pipelined processor: lw r4, 100 (r2) add r5, r2, r3 sub r6, r4, r5 and r7, r2, r5 I. Identify all the data dependencies in the above instruction sequence. For each dependency, indicate the two instructions and the register that causes the dependency. I Assume that the pipelined uses full forwarding. Draw a pipelined diagram that represents the flow of instructions through the pipeline during each clock cycle. Indicate forwarding by arrows

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