Question

The initial state of Q.Q.Q2Q3 is 0000. As it has 4 flip flops, make a time diagram with the clock CK, CLR, Qo, Q1, Q2,Q3 for 16 cycles. Explain what the circuit does. Logic 1 c oa oºo- HH WE L.PRO EOCK LOCK TOCK ck Like 4k eta | 4

Answer 1

The initial state of 0.9, 020₂ 4 00oo. And this has 4 flip flops. Now we have to mane a firing diagram with the clock CK, CLR, Oo, Q,,º,,03 481 16 cycles a Bo Ouled p2 103 Aogic IT Il О ИНІ T 0 K al This is a negative edge triggered clock pulse. And PR is preset and clh is clear which are asynchronous inputs. Now the timing diagram with clock ck, CLR, ao, 8, Q₂, Q3 for 16 cycles is

CK Eto othLOUILIB 142 list link etimolito liyo fervositorze TE Q, _0 ori Yoon ito 0:0 oi or Q._ooooiii ito 0:0:00 Olī 43– 0 0 0 0 0 0 0 0 I Moo 0 0 0 0 CIR ! i II i II iloĪ I 1 and az is I but as his a those SHOXE Q, must be are seset to 'o CLR = a, O₃ upto 10th clock pulse uR is I but @, will be I and my will be l are cleared after 10th Clock P = 111 =0 Soal to o. 9th clock pulse O So all states

The timing diagram is shown for 16 clock cycles And this arcuit is nothing but ana ou counter which counts from oto counts from o toq and whenever Q, and a becomes, I then au the states will be cleared to o end again the courd starts fromo. Here Q; and Oy are connected to NAND gate and wand gate output is given to cur signal so whenever Q, and Q3 are high, dr will be o and all the states are cleared to o