Code::
TEST BENCH ::
OUTPUT:
MONITOR OUTPUT:
CODE ::
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module mux_four_one( s, i , y );
input [1:0] s; //declaring input and
output ports
input [3:0] i;
output y;
wire [3:0] k;
assign k[0] = (~s[1])&(~s[0])&i[0];
//from mux output expression
assign k[1] = (~s[1])&s[0]& i[1];
assign k[2] = s[1] & (~s[0])& i[2];
assign k[3] = s[1] & s[0]& i[3];
assign y = k[0]+k[1]+k[2]+k[3]; //final output
endmodule
TEST BENCH
CODE::
`timescale 1ns / 1ps
module mux_four();
reg [1:0] s;
reg [3:0] i;
wire y;
integer f;
mux_four_one
n(s,i,y);
//instantiation
initial
begin
#2 $monitor("i = %b, | select = %b | y = %b
",i,s,y);
//displaying output with monitor
end
initial
begin
for(f=0; f<16; f
=f+1) //giving
inputs from for lopp
begin
i = f;
#5 s = 0
; //changing s
values
#5 s
=1;
#5 s =
2;
#5 s =
3;
end
end
endmodule
please all the stips Q1-4-to-1 MUX (Dataflow Modeling) use Veirlog: 1-use verilog HDL 2-Dataflow level Modeling...
in modelsim
Q1-4-to-1 MUX (Dataflow Modeling) use Veirlog: 1-use verilog 2-Dataflow level Modeling. 3-all the testbench no shortcut, allowed to use loop for testbench. 4-important show modelsim code,testbench,wave form.
Building and testing basic combinational circuits using Verilog HDL Description: Build and test the following circuits using gate-level modeling in Verilog HDL 1.3-input majority function 2.Conditional inverter (see the table below: x - control input, y -data input). Do NOT use XOR gates for the implementation. Output 3. Two-input multiplexer (see the table below: x.y -data inputs, z- control input) Output 4. 1-bit half adder. 5. 1-bit full adder by cascading two half adders 6.1-bit full adder directly (as in...
Write structural/heirarcherical Verilog to design 8 to 1 MUX using 2 to 1 and 4 to 1 MUX use wires
Building and testing basic combinational circuits using Verilog HDL Description: Build and test the following circuits using gate-level modeling in Verilog HDL. 1. 3-input majority function. 2. Conditional inverter (see the table below: x - control input, y - data input). Do NOT use XOR gates for the implementation. x y Output 0 y 1 y' 3. Two-input multiplexer (see the table below: x,y - data inputs, z - control input). z Output 0 x 1 y 4. 1-bit half...
Verilog code and wave. Please explain :)
§ If you use flipflops, you might need to handle ‘setup time’
for the flipflop. Also, you might need to initialize all input
signals.
Problem 3 [20 ptsl Design a testbench for 6-bit subtractor. Use at least 10 test cases. Submit your codes and test results (waveforms) with your testbench. You can use your Verilog code from Lab #1, or use the one posted on Canvas.
Problem 3 [20 ptsl Design a testbench...
why its 4-to-1 mux behavioral?
What does the logic circuit represented by the following Verilog module do, and what Verilog description style does it use? // My Verilog module #1 module mymodl ( x, d, q) input[1:0] x;input[3:0] d;output q; reg q; wire [1:0] x; wire [3:0] d; always ( x or d) begin case ( x ) 1 : q=d[1]; 2 : g=d[2]; 3 q d[3]; endcase end endmodule
1) Using Verilog behavioral modeling, describe an n-bit circuit that has four n-bit unsigned inputs A B, C, and D, and two control inputs C1, and CO. The circuit produces an n+1-bit output Y according to the following table: (No delavs) 120 marks CI CO Function 1 Y MAX (A,B,C,D) , i.e. Y equals the maximum of the four inputs 0 | Y 〈 MIN (A,B,C,D), i.e. Y, equals the minimum of the four inputs 1 YAVERAGE (A,B.C,D), i.e. Y...
Please solve Q1 and Q2
Complete the following homework problems. Show all work (making answers for clarity sure it is legible) and circle all Problem 1 w3 X A w4 w1 C D Y w2 Determine Boolean functions for intermediate outputs wl,w2,w3, and w4 as well as the output signals X and Y. b) a) Construct a truth table showing the intermediate outputs wl,w2,w3, and w4 as well as the output signals X and Y Use K-maps to find simplified...
can you please code a VHDL testbench and source code for a 2-to-1 mux, any equation you want to work with is fine thank you
1. Write a Verilog module called myNot to implement the logic NOT gate. 2. Write a test bench to test the myNot module created in step 10. Simulate the circuit using Sim and analyze the resulting waveform. 3. Take full screenshots of the source code of myNot module, the test bench Verilog file, and resulting simulation waveforms to be included in the lab report. Also include your waveform analysis in the lab report.