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1. Write a Verilog module called myNot to implement the logic NOT gate. 2. Write a test bench to test the myNot module create

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Answer #1

1.

ANSWER:

GIVEN THAT:

WRITING A VERILOG MODULE PROGRAM:

THE CODEING FOR 2 INPUT LOGIC AND GATE:

module myAnd(a,b,y);
input a,b; //input declaration and each are 1 bit
output wire y; //output y and it is also 1 bit
assign y=a&b;  
endmodule

2.

WRITING THE TEST BENCH PROGRAM:

module myAnd_tb;
reg a,b;
wire y;
myAnd z1(a,b,y); //module instantiation of and logic gate
initial
begin
#10 a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
endmodule

3.

THE SCREENSHOTS OF THE SOURCE CODE:

THE OUTPUT WAVE FROM:

Tsu 05 Tsu 0 Value Name 20.400 ns

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