Homework Answers
![select[1] select[0] d[0] d[2] d[3]](http://img.homeworklib.com/questions/529e8380-bef7-11ea-93fd-b73d18a819a0.png?x-oss-process=image/resize,w_560)
Code::
TEST BENCH ::
OUTPUT:
MONITOR OUTPUT:
CODE ::
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module mux_four_one( s, i , y );
input [1:0] s; //declaring input and
output ports
input [3:0] i;
output y;
wire [3:0] k;
assign k[0] = (~s[1])&(~s[0])&i[0];
//from mux output expression
assign k[1] = (~s[1])&s[0]& i[1];
assign k[2] = s[1] & (~s[0])& i[2];
assign k[3] = s[1] & s[0]& i[3];
assign y = k[0]+k[1]+k[2]+k[3]; //final output
endmodule
TEST BENCH
CODE::
`timescale 1ns / 1ps
module mux_four();
reg [1:0] s;
reg [3:0] i;
wire y;
integer f;
mux_four_one
n(s,i,y);
//instantiation
initial
begin
#2 $monitor("i = %b, | select = %b | y = %b
",i,s,y);
//displaying output with monitor
end
initial
begin
for(f=0; f<16; f
=f+1) //giving
inputs from for lopp
begin
i = f;
#5 s = 0
; //changing s
values
#5 s
=1;
#5 s =
2;
#5 s =
3;
end
end
endmodule
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in modelsim
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