Question

Could you help me understand what happening in this function, also adjust it to have a  period of 2 seconds and duty cycle 50%

module complexDivider (clk50Mhz, slowclk) input clk50Mhz;//fast clock output slowClk;1/slow clock reg [26:01 counter; initial begin counter0; end always (posedge clk50Mhz) begin if (counter == 25000000) begin counter <= 1; end else begin counter <= counter + 1; end end endmodule

Answer 1

`timescale 1ns/1ps

module complexDivider (clk50Mhz, slowClk);
input      clk50Mhz;   // Input Fast clock
output reg slowClk;    // Output Slow Clock

reg [26:0] counter;

initial
begin           
   counter = 0; // Initial value of counter is 0 as No reset is given
   slowClk = 0; // Initial value of slowClk is 0 else it will drive x
end

always @(posedge clk50Mhz)
begin
//   if (counter == 25000000) begin // this counter value given a slowClk of 1 sec with 50% duty cycle
   if (counter == 50000000) begin // if reaches 50 * (10^6), slowClk is of 2sec with 50% duty cycle
        counter <= 1;
        slowClk <= ~slowClk;       // slowClk toggles when then counter is reached
   end
   else begin
        counter <= counter + 1'b1; // else counter keeps on incrementing
   end
end

endmodule

module testbench;
reg   clk50Mhz;
wire slowClk;

complexDivider DUT (.clk50Mhz(clk50Mhz), .slowClk(slowClk));

always #10 clk50Mhz = !clk50Mhz;

initial
begin
     clk50Mhz = 1'b0;
     #2000000000;
     $finish;
end

initial
begin
     $recordfile("file1.trn");
     $recordvars();
end

endmodule