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3. Design the RGi and Ro2 bias string such that FET operates in the saturation mode with Ip 300 HA and the gate-to-ground input resistance, Rin , is 100 kΩ VIN-0.9 V and Kn-275 μΑ/V2 . (20 points) 5 V 5 V Ra1 V i R62 Rs > 4.3ΚΩ
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