a) A memory unit has 28-bit address lines and 64-bit input/output data lines. How many bytes...
a) A memory unit has 28-bit address lines and 64-bit input/output data lines. How many bytes of data can this memory hold? How many words does it contain, and how large is each word?
b) A memory unit consists of 32M words of 16-bit each. How many bits wide address lines and input-output data lines are needed to access this memory?
c) A memory unit consists of 512K bytes of data. How many bits wide address lines are needed to access this memory if the word size is 16 bit? If the word size is 64 bit?
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Homework Answers
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a) A memory unit has 28-bit address lines and 64-bit
input/output data lines. How many bytes...
A (word, bit, block, byte) or (Sector, cache line, page, row) is the unit of data...
A (word, bit, block, byte) or (Sector, cache line, page, row) is the unit of data transferred between cache, memory and the processor. A common size for a block is (64, 16, 32, 4k, 512) (bytes, lines, words, bits)
Memory organization a) Suppose that a 32MB system memory is built from 32 1MB RAM chips. How many...
Memory organization a) Suppose that a 32MB system memory is built from 32 1MB RAM chips. How many address lines are needed to select one of the memory chips? Suppose a system has a byte-addressable memory size of 4GB. How many bits are required for each address? Suppose that a system uses 16-bit memory words and its memory built from 32 1Mx 8 RAM chips. How large, in words, is the memory on this system? Suppose that a system uses...
Problem #1 (25 points) Address Space, Memory Consider a hypothetical 18-bit processor called HYP18 with all...
Problem #1 (25 points) Address Space, Memory Consider a hypothetical 18-bit processor called HYP18 with all registers, including PC and SP, being 18 bits long. The smallest addressable unit in memory is an 8-bit byte. A. (4 points) What is the size of HYP18's address space in bytes and KB? How many address lines does HYP18 require? Address space: Bytes Address space: KB (KiloBytes). Address bus lines: B. (6 points) Assume that first quarter of the address space is dedicated...
A computer has a memory space of 16 GB. a) How many address lines are required...
A computer has a memory space of 16 GB. a) How many address lines are required to span this address space, assuming it is byte- addressed? b) This computer has a block of 4 GB 32-bit-wide memory built using 512 MB static RAM chips that are each 8 bits wide. How many RAM chips are required to implement the memory?
Question 3. A computer has a memory space of 16 GB. a) How many address lines...
Question 3. A computer has a memory space of 16 GB. a) How many address lines are required to span this address space, assuming it is byte- addressed? b) This computer has a block of 4 GB 32-bit-wide memory built using 512 MB static RAM chips that are each 8 bits wide. How many RAM chips are required to implement the memory?
Exercise l: Suppose that we have a virtual memory space of 28 bytes for a given process and physical memory of 4 page frames. There is no cache. Suppose that pages are 32 bytes in length. 1) How...
Exercise l: Suppose that we have a virtual memory space of 28 bytes for a given process and physical memory of 4 page frames. There is no cache. Suppose that pages are 32 bytes in length. 1) How many bits the virtual address contain? How many bits the physical address contain? bs Suppose now that some pages from the process have been brought into main memory as shown in the following figure: Virtual memory Physical memory Page table Frame #...
1. A cache holds 64 words where each word is 4 bytes. Assume a 32 bit...
1. A cache holds 64 words where each word is 4 bytes. Assume a 32 bit address. There are four different caches a. A direct-mapped cache with block size = 16 words b. 2-way set-associative cache with block size = 8 words c. 4-way set-associative cache with block size=4 words d. A fully associative cache with block size = 16 words. Complete the table for each cache. Cache a Cache be Cache Cache de 16 Number of bits needed for...
A computer with a 24‐bit address bus has a main memory of size 16 MB and...
A computer with a 24‐bit address bus has a main memory of size 16 MB and a cache size of 64 KB. The word length is two bytes. a. What is the address format for a direct mapped cache with a line size of 32 words? b. What is the address format for a fully associative cache with a line size of 32 words? c. What is the address format for a 4‐way set associative cache with a line size...
Question 3: Consider a 32-bit physical address memory system with block size 16 bytes and a...
Question 3: Consider a 32-bit physical address memory system with block size 16 bytes and a 32 blocks direct mapped cache. The cache is initially empty. The following decimal memory addresses are referenced 1020, 1006, 1022, 5106, 994, and 2019 Map the addresses to cache blocks and indicate whether hit or miss. Note: You must use the hexadecimal approach in solving this question. You must also show the computations of dividing the memory address into tag bits, cache index bits,...
7. A computer has a memory space of 8 GB. a) How many address lines are...
7. A computer has a memory space of 8 GB. a) How many address lines are required to span this address space, assuming it is byte-addressed? b) This computer has a block of 2 GB 32-bit-wide memory built using 512 MB static RAM chips that are each 8 bits wide. How many RAM chips are required to implement the memory?
Memory organization a) Suppose that a 32MB system memory is built from 32 1MB RAM chips. How many address lines are needed to select one of the memory chips? Suppose a system has a byte-addressable memory size of 4GB. How many bits are required for each address? Suppose that a system uses 16-bit memory words and its memory built from 32 1Mx 8 RAM chips. How large, in words, is the memory on this system? Suppose that a system uses...
Problem #1 (25 points) Address Space, Memory Consider a hypothetical 18-bit processor called HYP18 with all registers, including PC and SP, being 18 bits long. The smallest addressable unit in memory is an 8-bit byte. A. (4 points) What is the size of HYP18's address space in bytes and KB? How many address lines does HYP18 require? Address space: Bytes Address space: KB (KiloBytes). Address bus lines: B. (6 points) Assume that first quarter of the address space is dedicated...
A computer has a memory space of 16 GB. a) How many address lines are required to span this address space, assuming it is byte- addressed? b) This computer has a block of 4 GB 32-bit-wide memory built using 512 MB static RAM chips that are each 8 bits wide. How many RAM chips are required to implement the memory?
Question 3. A computer has a memory space of 16 GB. a) How many address lines are required to span this address space, assuming it is byte- addressed? b) This computer has a block of 4 GB 32-bit-wide memory built using 512 MB static RAM chips that are each 8 bits wide. How many RAM chips are required to implement the memory?
Exercise l: Suppose that we have a virtual memory space of 28 bytes for a given process and physical memory of 4 page frames. There is no cache. Suppose that pages are 32 bytes in length. 1) How many bits the virtual address contain? How many bits the physical address contain? bs Suppose now that some pages from the process have been brought into main memory as shown in the following figure: Virtual memory Physical memory Page table Frame #...
1. A cache holds 64 words where each word is 4 bytes. Assume a 32 bit address. There are four different caches a. A direct-mapped cache with block size = 16 words b. 2-way set-associative cache with block size = 8 words c. 4-way set-associative cache with block size=4 words d. A fully associative cache with block size = 16 words. Complete the table for each cache. Cache a Cache be Cache Cache de 16 Number of bits needed for...
Question 3: Consider a 32-bit physical address memory system with block size 16 bytes and a 32 blocks direct mapped cache. The cache is initially empty. The following decimal memory addresses are referenced 1020, 1006, 1022, 5106, 994, and 2019 Map the addresses to cache blocks and indicate whether hit or miss. Note: You must use the hexadecimal approach in solving this question. You must also show the computations of dividing the memory address into tag bits, cache index bits,...
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