In the lecture we demonstrated how an active low, synchronous clear feature can be synthesized into a D flip-flop. For this task, please synthesize a D flip-flop that has an active low, synchronous preset feature added to it. Label the preset input signal as “preset_n”.
The truth table of the D flip flop is
CLK | D | Qn+1 |
0 | 0 | Qn |
0 | 1 | Qn |
1 | 0 | 0 |
1 | 1 | 1 |
for a high clock 1 Qn+1= D
The preset signal will force Qn+1 to 1 irrespective of clock and D.
Qn | Preset_n(bar) | Qn+1 | Qn+1(bar) |
0 | 0 | 1 | 0 |
0 | 1 | 0 | 1 |
1 | 0 | 1 | 0 |
1 | 1 | 1 | 0 |
Verilog code for the synthesis of D flip flop with Preset_n.
module dff_syspr (D, clk, preset_n, q);
input D, clk, preset_n;
output q;
reg q;
always @ (posedge clk)
if (~preset_n)
q = 1'b1;
else
q = data;
endmodule
In the lecture we demonstrated how an active low, synchronous clear feature can be synthesized into...
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