Suppose a real-time computer system has a 16-bit data and address busses. What test patterns are necessary and sufficient to test the address and data lines as well as the RAM cells?
A 16-bit CPU operates on 16 bits of data at a time. That is, the internal registers and data bus are in blocks of 16 bit, so each register has 16 bits, and data is moved around in chunks of 16 bits. Now, with a 16-bit CPU, it is 16 bits per register and data is moved around in chunks of only16 bit. The memory size is 2^16.
One memory "cell" actually contains either a 0 or a 1. It is only one bit. They are grouped into words, and CPU access the memory either as whole words. However, in the case of a number of chips, it is as portions of words.
So a 16-bit CPU works with 16-bit words. From the RAM chip's perspective, a word is the size of its data interface, so a 16-bit RAM chip has 16-bit words.
For your question, a 16-bit CPU and 16-bit RAM or more commonly, by adding multiple RAM chips in parallel, for example, a 16-bit CPU and four 4-bit RAM chips - each RAM chip handling a quarter of the data lines is possible. Depening on the size of patterns size will vary. In this case 16 bit. (The is same for RAM cells.). I hope you got the answer.
Suppose a real-time computer system has a 16-bit data and address busses. What test patterns are...
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