Question

A specific type of bit-level manipulation consists in setting or clearing one single bit in a multi-bit value, given its index and its new value. This operation can be implemented in hardware by a BitSet circuit with the following interface:

• Input x is a 4-bit value representing the original value.
• Output y is a 4-bit value representing the modified value, after the bit-set operation.
• Input index is a 2-bit value, ranging from 0 to 3, indicating the index of the bit to modify.
• Input value is a 1-bit value set to 0 or 1, indicating the value that bit index should take in output y. Every other bit in y should match the corresponding bit in x.

a) Show a hierarchical design of a 4-bit BitSet circuit using any kind of combinational logic blocks (MUX, Decoder, etc). For each reused logic block, specify its exact name and size, and label its complete interface. Label the interface of the BitSet circuit, too, matching the inputs and output listed above.

b) Write a Verilog module for the BitSet circuit using a structural model. If your circuit uses any auxiliary combinational block (multiplexer, decoder, …) you can use any other implementation model for its Verilog module (dataflow or behavioral).

c) Write a Verilog test-bench for your circuit, exploring at least four different combinations
for the inputs.

Answer 1

the design of the circuit is shown below:

the decoder selects the bit at which the change needs to be made and the mux routes the changed output to the selected bit and rest remain unchanged

the Verilog HDL module for the following is shown below:

// Code your design here
module design1(x,y,index,value);
input [3:0] x;// 4 bit wide inputs x
input [1:0] index; // 2 bit wide input index
input value;// 1bit wide input value
output reg [3:0] y;// output 4 bit wide
wire [3:0] x_sel;
decoder d1(index,x_sel);
mux m3({value,x[3]},x_sel[3],y[3]);
mux m2({value,x[2]},x_sel[2],y[2]);
mux m1({value,x[1]},x_sel[1],y[1]);
mux m0({value,x[0]},x_sel[0],y[0]);
endmodule

module decoder(index,x_sel);
input [1:0] index;
output reg [3:0] x_sel;
  
always@(*)
begin
case(index)
0: x_sel=1;//0001
1:x_sel=2;//0010
2:x_sel=4;//0100
3: x_sel=8;//1000
endcase
end
endmodule
module mux(i,sel,y);
input [1:0] i;
input sel;
output y;
  
assign y=sel?i[1]:i[0];
endmodule

testbench:

// Code your testbench here
// or browse Examples
module test();
reg [3:0] x;
reg [1:0] index;
reg value;
wire [3:0] y;
design1 d1(.*);// design instanciation
initial
begin// sending inputs
x=4'b1010;value=1;index=0;
#2 index=0;
#2 index=1;
#2 index=2;
#2 index=3;
#2 x=4'b1101;
#2index=0;
#2 index=1;
#2 index=2;
end
initial
begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule

waveform: