Question

Pro blem 2 VHDL Coding complete the following VHDL model for the given logic diagram by writing a VHDL architecture. (15 points) orl (30) -1 antl (10) r丈 dk

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity model is
   port (   clk, rst    : in std_logic;
       cntrl       : in std_logic_vector(1 downto 0);
       out1, out2   : out std_logic_vector(3 downto 0)
   );
end model;

architecture arch of model is

signal reg1, reg2   : std_logic_vector(3 downto 0);

begin

process (clk, rst)

begin

   if (rst = '1') then
       reg1 <= "0000";
       reg2 <= "0000";
   else
       if rising_edge(clk) then
           case (cntrl) is
               when "00"=>    reg1 <= reg1 + reg2;
                       reg2 <= reg2 - 1;
               when "01"=>    reg1 <= reg1 - reg2;
                       reg2 <= reg2 - 1;
               when "10"=>    reg1 <= reg1 + 1;
                       reg2 <= reg2 - 1;
               when "11"=>    reg1 <= reg1 - 1;
                       reg2 <= reg2 - 1;
               when others=>   null;
           end case;
       end if;
   end if;

out1 <= reg1;
out2 <= reg2;

end process;

end arch;

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