Question

f) Draw the waveform for the CL.K signal in following process 50 m(5%) Clock_gen: process CLK <=V'; wait for 10 ns; CL.K <='l'; wait for 20 ns, wait; end process clock_gen 10 ns g) If you have been asked to write a testbench for your design (for this system), what of the following you should include (5%) a) Process to generate Stimulus (for the inputs and the outputs), and a Component of your design (Unit under test) (5%) Process to generate clock Process to generate ASREST signal A and B A,B, and C b) c) d) e)

Answer 1

r) CLK Sigru, in flowing Pol iven thal Clock.gen: Pro begin ,,-b wait fov 10ns, CLK oal t end mot Clotk@の 。 Jn the above process use can note thok CLK Signal 10 Vivo V9 Dual Rear Camera

Duay cujlepua.dqu 가 CL.k ir knoon a, Th tout+마 Rons 3a4 Dual Rear Camera