Question

Experiment #3 Design and create simulation waveform for an 8-bit up/down synchronous (rising edge of clock) binary counter using Verilog Remember that your testbench can include statements such as always begin #10 clock="clock; end which specifies that the clock (reg) should toggle every 10 nSec

Answer 1

CODE:

module up_down_counter(input clk, reset,UpOrDown, output[7:0] Count
);

reg [7 : 0] Count = 0;
  
always @(posedge(clk) or posedge(reset))
begin
if(reset == 1)
Count <= 0;
else
if(UpOrDown == 1) //Up mode selected
if(Count == 255)
Count <= 0;
else
Count <= Count + 1; //Incremend Counter
else //Down mode selected
if(Count == 0)
Count <= 255;
else
Count <= Count - 1; //Decrement counter
end
  
end module

TESTBENCH:

module tb_counter;

// Inputs
reg Clk;
reg reset;
reg UpOrDown;

// Outputs
wire [7:0] Count;

// Instantiate the Unit Under Test (UUT)
upordown_counter uut (
.Clk(Clk),
.reset(reset),
.UpOrDown(UpOrDown),
.Count(Count)
);

//Generate clock with 10 ns clk period.
initial Clk = 0;
always #5 Clk = ~Clk;
  
initial begin
// Apply Inputs
reset = 0;
UpOrDown = 0;
#300;
UpOrDown = 1;
#300;
reset = 1;
UpOrDown = 0;
#100;
reset = 0;
end
  
endmodule