7.9 Assume that the 2-input NAND gate in Problem 7.8 is driving a 0.01pF load. Use hand calculations to estimate tPLH and tPHL. Do not forget to add in the parasitic capacitances extracted from your layout! Check your answer with SPICE. Use:
• kn’ = 20 µA/V2
• kp’ = 10 µA/V2
• VTn = |VTp| = 1.0 V
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