7.8 Use a layout editor (e.g., Magic) to lay out a two-input CMOS NAND gate. All devices have W = 10 µm. N-channel transistors have Leff= 1 µm and p-channel transistors have Leff = 2 µm. You can calculate the drawn channel lengths by assuming that LD= 0.25µm. After you lay out the gate use the design rule checker. Finally, you should have the layout editor perform parasitic capacitance extraction.
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