7.13 Consider a fully complementary CMOS transmission gate with its input terminal tied to ground (0 V) while the other non-gate terminal is tied to a 1pF load capacitor initially charged to 5 V. Use the VT0, k’p, and k’n values in Problem 7.12. At t = 0, both transistors are fully turned on by clock signals to start the discharge of the capacitor.
(a) Plot the effective resistance of this transmission gate as a function of capacitor voltage when (W/L)P = 50 and (W/L)n = 40. From the plot find the average value of the resistance. Then calculate the RC delay for the capacitor voltage to change from 5 V to 2.5 V. This can be found by solving the RC-circuit differential equation.
(b) Verify your answer to part (a) by using SPICE simulation. The source/drain parasitic capacitances can be neglected.
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