7.3 Analytical expressions for Vth(logic) have been derived in Chapter 7 for the CMOS NOR2 gate. Now consider CMOS NAND2 gate for the following cases assuming kp = kn = 100 µA/V2:
• two inputs switching simultaneously
• top nMOST switching while the bottom NMOST’s gate is tied to VDD
• top nMOST gate is tied to VDD and the gate input of the bottom nMOST is changing
(a) Derive an analytical expression for Vth corresponding to the first case. Also find the Vth value for the first case for VDD=5 V when the magnitudes of threshold voltages are same at 1V with γ = 0.
(b) Determine Vth for all three cases by using SPICE.
(c) For Cload= 0.2 pF calculate 50% delays (low-to-high and high-to-low propagation delays) for ideal pulse input signal for each of the three cases by assuming that Cload includes all the internal parasitic capacitances. Verify the results using SPICE.
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