7.1 A CMOS circuit was laid out based on a company X’s 3 µm design rules as shown in Fig....

7.1 A CMOS circuit was laid out based on a company X’s 3 µm design rules as shown in Fig. P7.1 with W_n =7µm and W_p=15µm.

Fig.P7.1

(a) From Fig. P7.1, determine the circuit configuration and draw the circuit diagram.

(b) For simple hand analysis, make the following assumptions:

i) Wiring parasitic capacitances and resistances are negligible.

ii) Device parameters are

iii) The total capacitance at node I is 0.6 pF.

iv) An ideal step-pulse signal is applied to CK terminal such that

v) At t = 0, the node voltage at I is zero.

vi) The input voltages at A₁, B₁ and B₂ are zero for 0 ≤ t ≤ T_W Find the minimum T_w that allows V_t to reach 2.5 V.