7.4 Write down the SPICE input description for transistor connections, source and drain parasitics in terms of areas, and perimeters for the layout shown in Example 7.2. Neglect the wiring capacitances in the poly silicon and metal runners. Default model names to be used for pMOS and nMOS are MODP and MODN. Assume L = 1 µm and Y = 10 µM for all transistors.
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