The diff-amp configuration shown in Figure P11.7 is biased at ±3 V. The maximum power diss...

The diff-amp configuration shown in Figure P11.7 is biased at ±3 V. The maximum power dissipation in the entire circuit is to be no more than 1.2 mW when v1 = v2 = 0. The available transistors have parameters: β = 120, VBE(on) = 0.7 V, and VA = ∞. Design the circuit to produce the maximum possible differential-mode voltage gain, but such that the common-mode input voltage can be within the range −1 ≤ vCM ≤ 1 V and the transistors are still biased in the forward-active region. What is the value of Ad ? What are the current and resistor values?