Consider the diff-amp configuration shown in Figure 11.7. Assume Q1 and Q2 are matched, let VA = ∞, and neglect base currents. Let IQ = 200 μA. (a) Design the circuit such that the differential-mode gain at vC1 is −150, the differential-mode gain at vC2 is +100, and the common-mode voltage is in the range −1.5 ≤ vCm ≤ 1.5 V. (b) Using the results of part (a), what are the minimum bias voltages V+ = −V− such that the input transistors always remain biased in the forward-active region.
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