Redesign the circuit in Figure 11.30 using a Widlar current source and bias voltages of ±5 V. The bias current IQ is to be no less than 100 μA and the total power dissipated in the circuit (including the current-source circuit) is to be no more than 10 mW. The diff-amp transistor parameters are the same as in Exercise Ex 11.10. The circuit is to provide a minimum loading effect when a second stage with an input resistance of R = 90 kΩ is connected to the diff-amp. Determine the differential mode voltage gain for this circuit.
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