(a) Design the circuit shown in Figure P11.44 such that vO = vD1 − vD2 = 1 V when v1 = −50 mV and v2 = +50 mV. The transistor parameters are VTN = 0.8 V, Kn =0.4 mA/V2, and λ = 0. (b) Using the results of part (a), determine the maximum common-mode input voltage.
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