Question

Look at the state diagram on the next slide. Note that the outputs are in red while the inputs are in black. There is one new input (goto_third) and two new 3-bit outputs (Out1 and Out2).

Question 2 (30%) 1. Look at the state diagram on the next slide. Note that the outputs are in red while the inputs are in black. There is one new input (goto_third) and two new 3-bit outputs (Out1 and Out2) 2. Write and hand in Verilog/VHDL code to implement the state machine in a way that does not have glitches. 4. Hand in a hand-drawn schematic of the logic that the Verilog/VHDL code is describing

Answer 1

`timescale 1ns / 1ps
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module state_machine(
input clk, restart, pause,
input goto_third,
output reg terminal,
output reg [2:0] out1, out2,
output reg even, odd
);
parameter    FIRST=3'b000,
               SECOND=3'b001,
               THIRD=3'b010,
               FOURTH=3'b011,
               FIFTH=3'b100;
              
reg [2:0] current_state, next_state;

always @(posedge clk)
begin
   if (restart)
       current_state <= FIRST;
   else
       current_state <= next_state;
end

always @(current_state, pause, goto_third)
begin
   case(current_state)
       FIRST       : if (pause) next_state <= FIRST; else next_state <= SECOND;
       SECOND   : if (pause) next_state <= SECOND; else next_state <= THIRD;
       THIRD       : if (pause) next_state <= THIRD; else next_state <= FOURTH;
       FOURTH   : if (pause) next_state <= FOURTH; else next_state <= FIFTH;
       FIFTH       : if (pause && !goto_third) next_state <= FIFTH; else if (goto_third) next_state <= THIRD; else if (!goto_third) next_state <= FIRST;
       default   : next_state <= FIRST;
   endcase
end

always @(current_state)
begin
   case(current_state)
       FIRST       : begin terminal <= 1'b0; out1 <= 3'd3; out2 <= 3'd2; even <= 1'b0; odd <= 1'b1; end
       SECOND   : begin terminal <= 1'b0; out1 <= 3'd5; out2 <= 3'd4; even <= 1'b1; odd <= 1'b0; end
       THIRD       : begin terminal <= 1'b0; out1 <= 3'd2; out2 <= 3'd7; even <= 1'b0; odd <= 1'b1; end
       FOURTH   : begin terminal <= 1'b0; out1 <= 3'd6; out2 <= 3'd3; even <= 1'b1; odd <= 1'b0; end
       FIFTH       : begin terminal <= 1'b1; out1 <= 3'd5; out2 <= 3'd2; even <= 1'b0; odd <= 1'b1; end
       default   : begin terminal <= 1'b0; out1 <= 3'd0; out2 <= 3'd0; even <= 1'b0; odd <= 1'b0; end
   endcase
end
endmodule
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