Question

VHDL code

FIRST ACTIVITY (100/100) RANDOM MEMORY ACCESS (RAM) EMULATOR: The following dircuit is a memory with 8 addresses, each address holding a 4-bit data. The memory positions are implemented by 4-bit registers. The resetn (active low) and clock signals are shared by all the registers. Data is written onto (or read from) one of the registers. wE rd 0 2 Memory Write (wr-rd = 1): The 4-bit input Din is written into one register. The address [2..0 signal selects the 3 register to be written. Here, the 7- segment display must show o. Example: if address "101, then Din is written into register 5. 3 HEX to 7 Memory Read (wr-rd=0): The MUX output appears on the 7-segment display (hex. vale). The address [2..01 signal selects the register from which data is read. For example, if address- 010, then data in register 2 appears on the 7-segment display. If data in register 2 is 1010", then the symbol A appears on the 7-segment display . 5 6 1 7

Answer 1

VHDL code for seven segment code library IEEE: use IEEE middot STD - LOGIC - 1164. ALL: use IEEE middot STD - LOGIC - ARITE. ALL: use IEEE middot STD - LOGIC - UNSIGNED. ALL: entity segment is port (clk: in STD - LOGIC: rst: in STD - LOGIC: digit: out STD - LOGIC - VECTOR (3 down to 0): display: out STD - LOGIC - VECTOR(7 down to 0)): end segment: architecture Behavioral of segment is SIGNAL state: integer ranger 1 to 16: = 1: SIGNAL data: STD - LOGIC - VECTOR (7 down to 0): SIGNAL clock: STD - LOGIC: being \r\n process (clk, rst) variable temp: integer range 1 to 999999999: being if (rst = �0�) then temp: = 1: elsif (rising - edge (clk)) then temp: = temp + 1: if (temp = 9999999) then clock < = not clock: temp: = 1: end if: end if: end process;