1. Explain the steps in the fetch–decode–execute cycle. Your explanation should include what is happening in the various registers.
2. Explain why, in MARIE, the MAR is only 12 bits wide and the AC is 16 bits wide. (Hint: Consider the difference between data and addresses.)
1) Steps in the fetch–decode–execute cycle
A) Fetch :-
The first step the CPU carries out is to fetch some data and instructions (program) from main memory then store them in its own internal temporary memory areas. These memory areas are called 'registers'.
This is called the 'fetch' part of the cycle.
For this to happen, the CPU makes use of a vital hardware path called the 'address bus'.
The CPU places the address of the next item to be fetched on to the address bus.
Data from this address then moves from main memory into the CPU by travelling along another hardware path called the 'data bus'.
B) Decode :-
The next step is for the CPU to make sense of the instruction it has just fetched.
This process is called 'decode'.
The CPU is designed to understand a specific set of commands. These are called the 'instruction set' of the CPU. Each make of CPU has a different instruction set.
The CPU decodes the instruction and prepares various areas within the chip in readiness of the next step.
C) Execution:-
This is the part of the cycle when data processing actually takes place. The instruction is carried out upon the data (executed). The result of this processing is stored in yet another register.
Once the execute stage is complete, the CPU sets itself up to begin another cycle once more.
2)
MARIE can handle 16-bit data, so the AC must be 16 bits wide. However, MARIE's memory is limited to 4096 address locations, so the MAR only needs to be 12 bits wide to hold the largest address.
1. Explain the steps in the fetch–decode–execute cycle. Your explanation should include what is happening in...
3. Use any one of the following instructions to explain the steps of the fetch-decode- execute cycle. Your explanation should include what is happening in the related registers. (10 points) Binary Contents of Hex Contents Memory Address Address Instruction of Memory 100 Load 104 0001000100000100 101 Add 105 102 Store 106 0100000100000110 103 Halt 104 0023 105 FFES 106 0000 1104 0011000100000101 4106 7000 0111000000000000 0000000000100011 0023 FEE9 3. Use any one of the following instructions to explain the steps...
Answer all elaborately or dont even attempt. 7. (4 points) Explain why, in MARIE, the MAR is only 12 bits wide while the AC is 16 bits wide. Hint: Consider the difference between data and addresses. 8. (24 points) Use a few sentences to answer each of the following questions. The answers can be found in section 4.1 to 4.7 in the textbook. 1) What purpose does the datapath in a CPU serve? 2) What does the control unit in...
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[20 pts] 5- Consider the following hypothetical 1-address assembly instruction called "Store Accumulator Indirect with Post-increment" of the form STA (x)- : M(M(x)) ← AC, M(x) ← M(x)+1 Suppose we want to implement this instruction on the pseudo-CPU discussed in class augmented with a temporary register TEMP. An instruction consists of 16 bits: A 4-bit opcode and a 12-bit address. All operands are 16 bits. PC and MAR each contain 12 bits. AC, MDR, and TEMP each contain 16 bits,...
I need answer for qustion (2) 1. One of the reasons why the MARE architecture is very inefficient is because it only has 1AC Assuming that you have access to many other ACs (AC, AC1, AC2, etc) Assume that in the new MARIE Architecture, you can do ADD 105 AC1 This means: Value @ x105 ACAC or suB 104 AC2 → This means: Valus @ x 104 + AC → AC2 How would your program (Lab #s, Question 1, also...
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