Question

Consider an FSM with one input I and three outputs x, y, and z. xyz should always exhibit the following sequence: 000, 001, 010, 100, repeat while I- 1. The output should change only on a rising clock edge. Make 000 the initial state. When I-0, the sequence should stop, holding the last value of xyz, when l #1 again, the sequence is to start over from 000 a. Draw a state diagram for the FSM b. Write the VHDL code for the FSM.

Answer 1

a)

b)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity stm is

port (

x,clk,reset:in std_logic;

Y:out std_logic_vector(2 downto 0)

);

end stm;

architecture Behavioral of stm is

type state is (s1,s10,s2,s20,s3,s30,s4,s40);

signal present_state,next_state:state;

begin

process(clk,reset)

begin

if (reset='1') then

present_state<=s1;

elsif rising_edge(clk) then

present_state<=next_state;

end if;

end process;

process(present_state,x)

begin

case (present_state) is

when s1 =>

if (x='0') then

next_state <= s10;

else

next_state <=s2;

end if;

when s10 =>

if (x='0') then

next_state <= s10;

else

next_state <=s1;

end if;

when s2 =>

if (x='0') then

next_state <= s20;

else

next_state <=s3;

end if;

when s20 =>

if (x='0') then

next_state <= s20;

else

next_state <=s1;

end if;

when s3 =>

if (x='0') then

next_state <= s30;

else

next_state <=s4;

end if;

when s30 =>

if (x='0') then

next_state <= s30;

else

next_state <=s1;

end if;

when s4 =>

if (x='0') then

next_state <= s40;

else

next_state <=s1;

end if;

when s40 =>

if (x='0') then

next_state <= s40;

else

next_state <=s1;

end if;

end case;

end process;

process(present_state)

begin

case (present_state) is

when s1 =>

Y<="000";

when s10 =>

Y<="000";

when s2 =>

Y<="001";

when s20 =>

Y<="001";

when s3 =>

Y<="010";

when s30 =>

Y<="010";

when s4 =>

Y<="100";

when s40 =>

Y<="100";

end case;

end process;

end Behavioral;