please explain Question 3 1. Write behavioral Verilog code to calculate the factorial of a 3-bit...

Question

Question

please explain

Question 3 1. Write behavioral Verilog code to calculate the factorial of a 3-bit unsigned number. (10 points)

2. Implement the following function using two 3-input-output lookup tables: f = abe + acid. (10 points)

engineering Electrical-Engineering

Add a comment Improve this question Transcribed image text

Answer 1

Answer #1

The code wil be
module factor (N, z);
input [2:0] N;
output [15:0] z;
reg [15:0] z;
integer i;
always @ (N)
begin
z = 1;
i = 0;
for(i=1;i<=N;i = i + 1)

Z = i* z;
end
endmodule
module test;
wire (15:0]z;
reg (2:0]N;
factor f(N,z);
initial
$monitor("fact (%d) = %d",N,z);
initial
begin
#0 N=7;
#5 N=6;
#5 N=5;
#5 N=4;
#5 N=3;
#5 N=2;
#5 N=1:

end
endmodule

The output

$C:\Users\HP.YO\Desktop>iverilog new1.vi C:\Users\HP.YO\Desktop>vvp a.out, fact (7) = 5040 fact (6) = 720 fact (5) = 120 fact$

Add a comment

Answer 2

Similar Homework Help Questions

Write 3-bit Gray code using jk-flip flop in verilog (behavioral code)

write 3-bit Gray code using jk-flip flop in verilog (behavioral code)
Write a behavioral code in Verilog to implement a RAM of 256 words with each word...

Write a behavioral code in Verilog to implement a RAM of 256 words with each word having 8 bits. RAM must have Enable, Read/Write pins and will have address bus, data bus (for both input and output). Write a testbench and demonstrate the working of all its read/write operations.
1) Using Verilog behavioral modeling, describe an n-bit circuit that has four n-bit unsigned inpu...

1) Using Verilog behavioral modeling, describe an n-bit circuit that has four n-bit unsigned inputs A B, C, and D, and two control inputs C1, and CO. The circuit produces an n+1-bit output Y according to the following table: (No delavs) 120 marks CI CO Function 1 Y MAX (A,B,C,D) , i.e. Y equals the maximum of the four inputs 0 | Y 〈 MIN (A,B,C,D), i.e. Y, equals the minimum of the four inputs 1 YAVERAGE (A,B.C,D), i.e. Y...

1) Using Verilog behavioral modeling, describe an n-bit circuit that has four n-bit unsigned inpu...

1) Using Verilog behavioral modeling, describe an n-bit circuit that has four n-bit unsigned inputs A B, C, and D, and two control inputs C1, and CO. The circuit produces an n+1-bit output Y according to the following table: (No delavs) 120 marks CI CO Function 1 Y MAX (A,B,C,D) , i.e. Y equals the maximum of the four inputs 0 | Y 〈 MIN (A,B,C,D), i.e. Y, equals the minimum of the four inputs 1 YAVERAGE (A,B.C,D), i.e. Y...
Please implement the function z(a, b, c) in Verilog HDL. Note: Please write your code in...

Please implement the function z(a, b, c) in Verilog HDL. Note: Please write your code in one module. ? = ? × ? + ?, where ? = ?^3 − ? ? = ???? ( 8/?×? , ?) Hint: output wire z; input wire a, b, c
please give the verilog code and explain in the form of comments. Part I Consider the...

please give the verilog code and explain in the form of comments. Part I Consider the circuit in Figure 1. It is a 4-bit synchronous counter (text Section 5.9.2) that uses four T-type flip- flops (text Section 5.5). The counter increments its value on each positive edge of the clock if the Enable signal is asserted. The counter is reset to 0 by setting the Clear b signal low - it is an active-low asynchronous clear. You are to implement...

Please code the following in Verilog: Write the HDL gate-level hierarchical description of a four-bit adder-subtractor...

Please code the following in Verilog: Write the HDL gate-level hierarchical description of a four-bit adder-subtractor for unsigned binary numbers similar to the following circuit. You can instantiate the four-bit full adder described in the following example code Figure 4.13a, 4-Bit adder-subtractor without overflow Inputs: 4-Bit A, 4-Bit B, and Mode M (0-add/1-subtract) Interfaces: Carry Bits C1, C2, C3 Outputs: Carry C (1 Bit, C4), Sum S (4 bit) Bo A FA FA FA FA module Add half (input a,...
Write an Verilog code for a 8-bit subtractor (Bits are in 1's complement) using the following:...

Write an Verilog code for a 8-bit subtractor (Bits are in 1's complement) using the following: 1. 5-bit parallel adder 2. 3-bit parallel adder The condition are as follows: 1. The Most Significant bits of the subtractor must be given to the 5-bit parallel adder. 2, The Least Significant bits of the subtractor must be given to the 3-bit parallel adder. 3. The input A will be assign to the switches with the least significant bit A[0] linked to SW0....
Verilog code and wave. Please explain :) § If you use flipflops, you might need to handle ‘setup ...

Verilog code and wave. Please explain :) § If you use flipflops, you might need to handle ‘setup time’ for the flipflop. Also, you might need to initialize all input signals. Problem 3 [20 ptsl Design a testbench for 6-bit subtractor. Use at least 10 test cases. Submit your codes and test results (waveforms) with your testbench. You can use your Verilog code from Lab #1, or use the one posted on Canvas. Problem 3 [20 ptsl Design a testbench...

Verilog HDL Design a logic module to multiply an 8-bit binary number A [0:7] by a...

Verilog HDL Design a logic module to multiply an 8-bit binary number A [0:7] by a 4-bit binary number N [0:3]. The multiply is started when M is asserted. The output F is asserted when the multiply is completed and the product P [0: 15] is available. The outputs need to remain valid until the next multiply command is given. Assume M is valid for several of your clock cycles and then is de-asserted. Implement the multiply using repeated addition...

please explain Question 3 1. Write behavioral Verilog code to calculate the factorial of a 3-bit...

Homework Answers

Add Answer to:
please explain Question 3 1. Write behavioral Verilog code to calculate the factorial of a 3-bit...

Post as a guest

Earn Coins

Write 3-bit Gray code using jk-flip flop in verilog (behavioral code)

Write a behavioral code in Verilog to implement a RAM of 256 words with each word...

1) Using Verilog behavioral modeling, describe an n-bit circuit that has four n-bit unsigned inpu...

1) Using Verilog behavioral modeling, describe an n-bit circuit that has four n-bit unsigned inpu...

Please implement the function z(a, b, c) in Verilog HDL. Note: Please write your code in...

please give the verilog code and explain in the form of comments. Part I Consider the...

Please code the following in Verilog: Write the HDL gate-level hierarchical description of a four-bit adder-subtractor...

Write an Verilog code for a 8-bit subtractor (Bits are in 1's complement) using the following:...

Verilog code and wave. Please explain :) § If you use flipflops, you might need to handle ‘setup ...

Verilog HDL Design a logic module to multiply an 8-bit binary number A [0:7] by a...

please explain Question 3 1. Write behavioral Verilog code to calculate the factorial of a 3-bit...

Homework Answers

Add Answer to: please explain Question 3 1. Write behavioral Verilog code to calculate the factorial of a 3-bit...

Post as a guest

Earn Coins

Add Answer to:
please explain Question 3 1. Write behavioral Verilog code to calculate the factorial of a 3-bit...