Question

8. Write a complete VHDL code for the 4-bit counter shown below. Reset synchronously returns the output state to 1010. The counting is synchronized to the rising edge of Clk. Reset 1010 0010 1110 1011

Answer 1

module counter(clock, reset, z);    // z becomes 1 when counter reaches 1010

input clock, reset;      // declaration of inputs

output reg z;             // declaration of output

reg [3:0] ps,ns;        // to store present state and next state, we need to declare it with reg

parameter s0=1010,s1=0010,s2=1011,s3=1110; // assigning counter states to s0,s1,s2,s3 respectively

always@(ps)     // always block for switching to next state in a counter and displaying output for each state

begin

case(ps)

s0 : begin

       z=1; ns=s1;

       end

s1 : begin

      z=0; ns=s2;

      end

s2 : begin

      z=0; ns=s3;

      end

s3 : begin

      z=0; ns=s0;

      end

end

endcase

always@(posedge clock) // always block for starting of the counter

if(reset)

      ps<=s0;    // initial it should in first state

else

      ps<=ns;    // if not reset, then next state becomes present state

end