Question

Write a Verilog module that implements the following Boolean equation:

f1 = a * b * c' + a * c + b * c

Simplify the above expression; write another module to implement it as f2.
Write a test bench to check whether f1 and f2 are identical with different values of a, b and c.

Answer 1

DESIGN MODULE FOR F1:

module f1mod(a,b,c,f1);

input a,b,c;

output f1;

  

assign f1= (a & b & ~c)|(a & c)+(b & c);

endmodule

TESTBENCH MODULE FOR F1:-

module tb();

reg a,b,c;

wire f1;

integer i;

f1mod f1m(a,b,c,f1);

initial begin

$monitor(" a=%b,b=%b,c=%b,f1=%b",a,b,c,f1);

end

initial begin

//FOR GENERATING ALL 8 COMBINATIONS OF INPUT.

for(i=0;i<8;i=i+1)

begin

{a,b,c}=i;#5;

end

end

  

endmodule

OUTPUT SCREENSHOT FOR F1:-

Simplifying F2:---

DESIGN MODULE FOR F2:-

module f2mod(a,b,c,f2);

input a,b,c;

output f2;

  

assign f2= (a & b)|(a & c)+(b & c);

endmodule

TESTBENCH MODULE FOR F2:-

module tb();

reg a,b,c;

wire f2;

integer i;

f2mod f2m(a,b,c,f2);

initial begin

$monitor(" a=%b,b=%b,c=%b,f2=%b",a,b,c,f2);

end

initial begin

//FOR GENERATING ALL 8 COMBINATIONS OF INPUT.

for(i=0;i<8;i=i+1)

begin

{a,b,c}=i;#5;

end

end

  

endmodule

OUTPUT SCREENSHOT FOR F2:-

BOTH OUPUT OF f1 AND f2 ARE SAME.