answer 6:
module FSM(X,Y,RED,GRN,reset,clk);
input X,Y,clk,reset;
output reg RED,GRN;
reg [1:0] state,nextstate;
always@(posedge clk)
begin
if(reset)
state<=0;
else
state<=nextstate;
end
always@(state)// output logic
begin
case(state)
0:begin RED=0;GRN=0; end
2:begin RED=1;GRN=0; end
3: begin GRN=1; RED=0; end
default: begin RED=0;GRN=0; end
endcase
end
always@(state,X,Y)// Nextstate logic
begin
case(state)
0: begin
if(X==0)
state<=2;
else
state<=3;
end
2: begin
if(X==0)
state<=2;
else
state<=3;
end
3:begin
if(Y==0)
state<=2;
else
state<=3;
end
default: state=0;
endcase
end
endmodule
answer 5:
module top(A,B,opcode,out,clk);// you need to add the control signals as per your register regisn and ALu design
input A,B;// please mention input width here with inputs
input opcode;// please specify the width of opcode
input clk;
output reg out; // output width needs to be mentioned here as per you modules
reg QA,QB;// note width should be mentioned in accordance with ur design parameters
wire out_alu;
register A1(A,clk,QA);//-- input A stored in register A1
register B1(B,clk,QB);//- input A stored in register A1
alu a1(QA,QB,opcode,out_alu);
register D1(out_alu,clk,out);
endmodule
5. (1 pt) Use Verilog port mapping to create a small accumulator-based processor using your 8-bit...
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