Assume for arithmetic, load/store, and branch instructions, a processor core has CPIs of 1,12 and 5...
Assume for arithmetic, load/store, and branch instructions, a processor core has CPIs of 1,12 and 5 respectively. Also assume that on a single processor core a program requires the execution of 2.56E9 arithmetic instructions, 1.28E9 load/store instructions, and 256.0E6 branch instructions. Assume all processor cores run at 2 GigaHertz. Assume that, as the program is parallelized to run over multiple processor cores, the number of load/store instructions per processor core is divided by .5 times p for all number of cores greater then 1, where p is the number of cores. Assume that the number of arithmetic and branch instructions per core stays the same.
a)Find the total execution time for the program on 1,2,4 cores
b)Find the relative speed up on 2,4 cores compared to one core
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Assume for arithmetic, load/store, and branch instructions, a
processor core has CPIs of 1,12 and 5...
Assume for arithmetic, load/store, and branch instructions, a processor has CPls of 3, 15, and 7, respectively. Also as...
Assume for arithmetic, load/store, and branch instructions, a processor has CPls of 3, 15, and 7, respectively. Also assume that on a single processor a program requires the execution of 3.12E9 arithmetic instructions, 1.75E9 load/store instructions, and 512Million branch instructions. Assume that each processor has a 2.5GHz clock frequency. Assume that, as the program is parallelized to run over multiple cores, the number of arithmetic and load/store instructions per processor divided by 0.8xp ( where p is the number of...
c. Performance: Company A's processor and Company B's processor are benchmarked on the same program. The...
c. Performance: Company A's processor and Company B's processor are benchmarked on the same program. The CPI of the component instructions that are executed in the program are shown above for each processor. Additionally, the number of instructions of each type is provided. Company A 5 Branch CPI Load/Store CPI Arithmetic CPI 7 1 Company B 4 Branch CPI Load/Store CPI Arithmetic CPI 9 1 Program Instruction Count Branch Load/Store Arithmetic CPL 1.2x109 1.67x1010 1.5x1011 i. Assume Company A has...
Given a processor that runs at 1GHz with the following: Instruction-------------- Frequency --------------Cycles Load & store ----------------25% --------------------10 arithmetic instructions----...
Given a processor that runs at 1GHz with the following: Instruction-------------- Frequency --------------Cycles Load & store ----------------25% --------------------10 arithmetic instructions------ 65% --------------------6 branch instructions -----------10%-------------------- 4 1) Calculate the CPI for the above. 2) Suppose the amount of registers are doubled, such that clock cycle time increases by 40%. What is the new clock speed (in GHz)? 3) Assume only the load & stores instructions are speed up by 5 times and their frequency is increased to 50% (Arithmetic instructions...
Problem 1 Assume that a processor with a clock rate of 1 GHz clock runs a...
Problem 1 Assume that a processor with a clock rate of 1 GHz clock runs a benchmark program w mix of instructions given in the table below. Instruction class CPI FP INT Load/Store (L/S) Branch Instruction count 50 x 106 110 x 106 50 x 106 10 x 106 By how much must the CPI of L/S instructions be improved if the program is to run two times faster?
A program that executes 12.3x107 instructions is run on a pipelined processor. The table below provides...
A program that executes 12.3x107 instructions is run on a pipelined processor. The table below provides the percentage of executed instructions for each type of instruction. Instruction Executed P ipeline CPU type instructions (%) w/o hazards ALU 29.4 Load 29.7 Store 14.7 Branch 26.2 2 (w/o prediction) 27% of the load instructions are followed by instructions that need the data being loaded, 47% of the branches are actually.not taken, please assume not taken prediction. a) Please determine the overall cycles...
Suppose we have developed new versions of a processor with the following characteristics: Version Voltage 1.5 V 1.2V Clock rate 2.4 GHz 3GHZ a) How much has the capacitive load varied between version...
Suppose we have developed new versions of a processor with the following characteristics: Version Voltage 1.5 V 1.2V Clock rate 2.4 GHz 3GHZ a) How much has the capacitive load varied between versions if the dynamic power has been reduced by 15%? Assuming that the capacitive load of version 2 is 70% the capacitive load of version 1, find the new voltage value for version 2 if the dynamic power of version 2 is reduced by 35% from version 1....
Assume an memory hierarchy with unified data and instruction memories, miss rate equal to 15%, miss penalty equal to 90 cycles, 25% Load/Store instructions, TLB miss ratio per TLB access equal to 6% a...
Assume an memory hierarchy with unified data and instruction memories, miss rate equal to 15%, miss penalty equal to 90 cycles, 25% Load/Store instructions, TLB miss ratio per TLB access equal to 6% and TLB miss penalty equal to 80 cycles. What is the realistic CPI of this system if the ideal CPI is 1.5? What is the speedup compared to not having TLB? What would be the speedup if the TLB could hold every entry?
computer analysis
Questions1. The function L is defined as L(1) = 2,L(2) = 1,L(3) = 3,L(4) = 4 and for n ≥ 4,L(n + 1) = L(n) + L(n − 1) + L(n − 2)L(n − 3)i.e., the (n + 1)-th value is given by the sum of the n-th, n − 1-th and n − 2-th values divided by the n − 3-th value.(a) Write an assembly program for computing the k-th value L(k), where k is an integer bigger than...
Group Project 1 The Micro-1 Processor Simulation <Micro-1 Computer> Here's the organization of a computer equipped...
Group Project 1 The Micro-1 Processor Simulation <Micro-1 Computer> Here's the organization of a computer equipped with a Micro-1 processor Memory contains an array of integer cells: int cell[] = new int[CAP]; where CAP is the capacity of memory. Initially this is set to 256. Internally, the Micro-1 processor is equipped with eight 32-bit data/address registers and two 32 bit control registers: PC, the program counter, contains the address of the next instruction to execute. IR, the instruction register, contains...
I need help with my very last assignment of this term PLEASE!!, and here are the instructions: After reading Chapter T...
I need help with my very last assignment of this term
PLEASE!!, and here are the instructions: After reading Chapter Two,
“Keys to Successful IT Governance,” from Roger Kroft and Guy
Scalzi’s book entitled, IT Governance in Hospitals and Health
Systems, please refer to the following assignment instructions
below.
This chapter consists of interviews with executives
identifying mistakes that are made when governing healthcare
information technology (IT). The chapter is broken down into
subheadings listing areas of importance to understand...
Assume for arithmetic, load/store, and branch instructions, a processor has CPls of 3, 15, and 7, respectively. Also assume that on a single processor a program requires the execution of 3.12E9 arithmetic instructions, 1.75E9 load/store instructions, and 512Million branch instructions. Assume that each processor has a 2.5GHz clock frequency. Assume that, as the program is parallelized to run over multiple cores, the number of arithmetic and load/store instructions per processor divided by 0.8xp ( where p is the number of...
c. Performance: Company A's processor and Company B's processor are benchmarked on the same program. The CPI of the component instructions that are executed in the program are shown above for each processor. Additionally, the number of instructions of each type is provided. Company A 5 Branch CPI Load/Store CPI Arithmetic CPI 7 1 Company B 4 Branch CPI Load/Store CPI Arithmetic CPI 9 1 Program Instruction Count Branch Load/Store Arithmetic CPL 1.2x109 1.67x1010 1.5x1011 i. Assume Company A has...
Problem 1 Assume that a processor with a clock rate of 1 GHz clock runs a benchmark program w mix of instructions given in the table below. Instruction class CPI FP INT Load/Store (L/S) Branch Instruction count 50 x 106 110 x 106 50 x 106 10 x 106 By how much must the CPI of L/S instructions be improved if the program is to run two times faster?
A program that executes 12.3x107 instructions is run on a pipelined processor. The table below provides the percentage of executed instructions for each type of instruction. Instruction Executed P ipeline CPU type instructions (%) w/o hazards ALU 29.4 Load 29.7 Store 14.7 Branch 26.2 2 (w/o prediction) 27% of the load instructions are followed by instructions that need the data being loaded, 47% of the branches are actually.not taken, please assume not taken prediction. a) Please determine the overall cycles...
Suppose we have developed new versions of a processor with the following characteristics: Version Voltage 1.5 V 1.2V Clock rate 2.4 GHz 3GHZ a) How much has the capacitive load varied between versions if the dynamic power has been reduced by 15%? Assuming that the capacitive load of version 2 is 70% the capacitive load of version 1, find the new voltage value for version 2 if the dynamic power of version 2 is reduced by 35% from version 1....
I need help with my very last assignment of this term
PLEASE!!, and here are the instructions: After reading Chapter Two,
“Keys to Successful IT Governance,” from Roger Kroft and Guy
Scalzi’s book entitled, IT Governance in Hospitals and Health
Systems, please refer to the following assignment instructions
below.
This chapter consists of interviews with executives
identifying mistakes that are made when governing healthcare
information technology (IT). The chapter is broken down into
subheadings listing areas of importance to understand...
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