Question

Consider the instruction formats of the basic comp

0 0
Add a comment Improve this question Transcribed image text
Answer #1

a)
Given Instruction is :

Hexadecimal : C450
Instruction(binary): 1100 0100 0101 0000 contains
Instruction RTL : M[450] <- R1 ;(consider C450)
So, xor operation between these two locations..
0000 1001 1000 0000 = 0890
1100 0100 0101 0000 = C450
----------------------------------
1100 1101 1101 0000 = cDD0
------------------------------------
In Hexadecimal: CDD0
In binary: 1100 1101 1101 0000

------------------------------------------------------------------------------------------------------------------------------

b)
Given data:
Hexadecimal: 4450
Binary instruction: 0100 0100 0101 0000

Instruction: M[450] <- R1 ;consider R1 = 4450H
Performing XOR operation..

0000 1001 1001 0000 ----> 0990
0100 0100 0101 0000 ----> 4450
-----------------------------------
0100 1101 1100 0000 ----> 4DC0

Final answer in
Hexadecimal : 4DC0
Binary: 0100 1101 1100 0000

-----------------------------------------------------------------------------------------
(c)
Given data
Hexadecimal : 7040
Binary: 0111 0000 0100 0000

RTL instruction
Ac <- 7040
Accumulator operation, so addition performing
0101 0000 0000 0111 ---> 5007
0111 0000 0100 0000 ---> 7040
----------------------------------
1100 0000 0100 0111 ----> C047
-------------------------------------
Final answer is:
Hexadecimal : C047
Binary : 1100 0000 0100 0111

Add a comment
Know the answer?
Add Answer to:
Consider the instruction formats of the basic computer in Fig. 5-5 and the list of instructions...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions
  • Consider a hypothetical computer with an instruction set of only two n-but instructions. The firs...

    Consider a hypothetical computer with an instruction set of only two n-but instructions. The first bit specifies the opcode, and the remaining bits specify one of the 2-1 n-bit words of main memory. The two instructions are as follows: SUBS X: Subtract the contents of location X from the accumulator, and store the result in location X and the accumulator JUMP X: Place address X in Program Counter A word in memory may contain either an instruction or a binary...

  • Question 20 5 pts Suppose a computer has 32-bit instructions. The instruction set consists of 64...

    Question 20 5 pts Suppose a computer has 32-bit instructions. The instruction set consists of 64 different operations. All instructions have an opcode and two address fields (allowing for two addresses). The first of these addresses must be a register direct address, and the second must be a memory address. Expanding opcodes are not used. The machine has 16 registers. What's the size of the largest memory space that can be addressed by this computer?Assume byte addressable memory.

  • Consider a hypothetical computer with an instruction set of only two n-bit instruc- tions.The first bit...

    Consider a hypothetical computer with an instruction set of only two n-bit instruc- tions.The first bit specifies the opcode, and the remaining bits specify one of the 2-1 n-bit words of main memory. The two instructions are as follows: 12.7 SUBS X Subtract the contents of location X from the accumulator, and store the result in location X and the accumulator. Place address X in the program counter JUMPX A word in main memory may contain either an instruction or...

  • pls both ans Question 20 5 pts Suppose a computer has 32-bit instructions. The instruction set...

    pls both ans Question 20 5 pts Suppose a computer has 32-bit instructions. The instruction set consists of 64 different operations. All instructions have an opcode and two address fields (allowing for two addresses). The first of these addresses must be a register direct address, and the second must be a memory address. Expanding opcodes are not used. The machine has 16 registers. How many bits can be used for the memory address? Question 21 5 pts Suppose we have...

  • 26. The is a group of bits that tells the computer to perform a specific operation...

    26. The is a group of bits that tells the computer to perform a specific operation A). program counter B). Opcode C). register D). microoperation 27. A condition called occurs in unsigned binary representation of a number when the result of an arithmetic operation is outside the range of allowable precision for the given number of bits. A). underflow B). 2's complement C). overflow D) bitwise complement 28. An iteration of the fetch-decode-execute cycle includes which of the following events?...

  • [20 pts] 5- Consider the following hypothetical 1-address assembly instruction called "Store Accumulator Indirect with Post-increment"...

    [20 pts] 5- Consider the following hypothetical 1-address assembly instruction called "Store Accumulator Indirect with Post-increment" of the form STA (x)- : M(M(x)) ← AC, M(x) ← M(x)+1 Suppose we want to implement this instruction on the pseudo-CPU discussed in class augmented with a temporary register TEMP. An instruction consists of 16 bits: A 4-bit opcode and a 12-bit address. All operands are 16 bits. PC and MAR each contain 12 bits. AC, MDR, and TEMP each contain 16 bits,...

  • QUESTION 21 Which one of the following PLC 5 addressing statements is NOT true? Input and...

    QUESTION 21 Which one of the following PLC 5 addressing statements is NOT true? Input and output (I/O) addressing connects a field device at a terminal on an I/O module to a bit location in the processor memory. A group is 16 input terminals (one 16 bit input word) and 16 output terminals (one 16 bit output word). Processors support up to 24 racks; the processor can be any one of the racks in the system. Terminals (called I/O points)...

  • 5 Exercises Now that everything is working you can try the following exercises. To complete them you will need to refer...

    5 Exercises Now that everything is working you can try the following exercises. To complete them you will need to refer to the documentation in Appendix A- The MiteASM Assembler and Appendix B - The MiteFPGA Processor. Write an assembly language program for an over counter for a cricket umpire. This should display a count on the 7-segment display. The count should increase by 1 when button 0 is 1. pressed. It should reset to 0 when button 1 is...

  • Group Project 1 The Micro-1 Processor Simulation <Micro-1 Computer> Here's the organization of a computer equipped...

    Group Project 1 The Micro-1 Processor Simulation <Micro-1 Computer> Here's the organization of a computer equipped with a Micro-1 processor Memory contains an array of integer cells: int cell[] = new int[CAP]; where CAP is the capacity of memory. Initially this is set to 256. Internally, the Micro-1 processor is equipped with eight 32-bit data/address registers and two 32 bit control registers: PC, the program counter, contains the address of the next instruction to execute. IR, the instruction register, contains...

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT