TABLE Sequencing element parameters
Setup Time | clk-to-Q Delay | D-to-Q Delay | Contamination Delay | Hold Time | |
Flip-Flops | 65 ps | 50 ps | n/a | 35 ps | 30 ps |
Latches | 25 ps | 50 ps | 40 ps | 35 ps | 30 ps |
For each of the following sequencing styles, determine the maximum logic propagation delay available within a 500 ps clock cycle. Assume there is zero clock skew and no time borrowing takes place.
a) Flip-flops
b) Two-phase transparent latches
c) Pulsed latches with 80 ps pulse width
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