TABLE Sequencing element parameters
| Setup Time | clk-to-Q Delay | D-to-Q Delay | Contamination Delay | Hold Time | |
| Flip-Flops | 65 ps | 50 ps | n/a | 35 ps | 30 ps |
| Latches | 25 ps | 50 ps | 40 ps | 35 ps | 30 ps |
A synchronizer uses a flip-flop with τs = 54 ps and T0 = 21 ps. Assuming the input toggles at 10 MHz and the setup time is negligible, what is the minimum clock period for which the mean time between failures exceeds 100 years?
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