TABLE Sequencing element parameters
Setup Time | clk-to-Q Delay | D-to-Q Delay | Contamination Delay | Hold Time | |
Flip-Flops | 65 ps | 50 ps | n/a | 35 ps | 30 ps |
Latches | 25 ps | 50 ps | 40 ps | 35 ps | 30 ps |
Design a fast pulsed latch. Make the gate capacitance on the clock and data inputs equal. Let the latch drive an output load of four identical latches. Simulate your latch and find the setup and hold times and clock-to-Q propagation and contamination delays. Express your results in FO4 inverter delays.
We need at least 10 more requests to produce the solution.
0 / 10 have requested this problem solution
The more requests, the faster the answer.