TABLE Sequencing element parameters
Setup Time | clk-to-Q Delay | D-to-Q Delay | Contamination Delay | Hold Time | |
Flip-Flops | 65 ps | 50 ps | n/a | 35 ps | 30 ps |
Latches | 25 ps | 50 ps | 40 ps | 35 ps | 30 ps |
Determine the minimum clock period at which the circuit in Figure will operate correctly for each of the following logic delays. Assume there is zero clock skew and that the latch delays are accounted for in the propagation delay
a) Δ 1 = 300 ps; Δ 2 = 400 ps; Δ 3 = 200 ps; Δ 4 = 350 ps
b) Δ 1 = 300 ps; Δ 2 = 400 ps; Δ 3 = 400 ps; Δ 4 = 550 ps
c) Δ 1 = 300 ps; Δ 2 = 900 ps; Δ 3 = 200 ps; Δ 4 = 350 ps
FIGURE : Another example path
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