TABLE Sequencing element parameters
Setup Time | clk-to-Q Delay | D-to-Q Delay | Contamination Delay | Hold Time | |
Flip-Flops | 65 ps | 50 ps | n/a | 35 ps | 30 ps |
Latches | 25 ps | 50 ps | 40 ps | 35 ps | 30 ps |
Using a simulator, compare the D-to-Q propagation delays of a conventional dynamic latch from Figure and a TSPC latch from Section 10.3.11. Assume each latch is loaded with a fanout of 4. Use 4 λ-wide clocked transistors and tune the other transistor sizes for least propagation delay.
FIGURE : Transparent latches
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