TABLE Sequencing element parameters
Setup Time | clk-to-Q Delay | D-to-Q Delay | Contamination Delay | Hold Time | |
Flip-Flops | 65 ps | 50 ps | n/a | 35 ps | 30 ps |
Latches | 25 ps | 50 ps | 40 ps | 35 ps | 30 ps |
Repeat Exercise if the clock skew between any two elements can be up to 50 ps.
Exercise
Determine the maximum logic propagation delay available in a cycle for a fourphase skew-tolerant domino pipeline using a 500 ps clock cycle. Assume there is zero clock skew.
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