Problem

TABLE Sequencing element parameters Setup Timeclk-to-Q DelayD-to-Q DelayContamination Dela...

TABLE Sequencing element parameters

	Setup Time	clk-to-Q Delay	D-to-Q Delay	Contamination Delay	Hold Time
Flip-Flops	65 ps	50 ps	n/a	35 ps	30 ps
Latches	25 ps	50 ps	40 ps	35 ps	30 ps

Using a simulator, find the setup and hold times of a TSPC latch under the assumptions of Exercise

Exercise
Using a simulator, compare the D-to-Q propagation delays of a conventional dynamic latch from Figure and a TSPC latch from Section 10.3.11. Assume each latch is loaded with a fanout of 4. Use 4 λ-wide clocked transistors and tune the other transistor sizes for least propagation delay.
FIGURE : Transparent latches