TABLE Sequencing element parameters
| Setup Time | clk-to-Q Delay | D-to-Q Delay | Contamination Delay | Hold Time | |
| Flip-Flops | 65 ps | 50 ps | n/a | 35 ps | 30 ps |
| Latches | 25 ps | 50 ps | 40 ps | 35 ps | 30 ps |
Repeat Exercise if the clock skew between any two elements can be up to 50 ps.
For each of the following sequencing styles, determine the minimum logic contamination delay in each clock cycle (or half-cycle, for two-phase latches). Assume there is zero clock skew.
a) Flip-flops
b) Two-phase transparent latches with 50% duty cycle clocks
c) Two-phase transparent latches with 60 ps of nonoverlap between phases
d) Pulsed latches with 80 ps pulse width
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