3.6 Consider a layout of an nMOS transistor shown in Fig.P3.6.The process parameters are:...

3.6 Consider a layout of an nMOS transistor shown in Fig.P3.6.

The process parameters are:

•N_D=2·10²⁰cm^-3

•N_A=1·10¹⁵cm^-3

•X_j = 0.5 μm

• L_D = 0.5 μm

•t_ox =0.05 μm

• V_T0=0.8 V

• Channel stop doping = 16.0 x (p-type substrate doping)

Find the effective drain parasitic capacitance when the drain node voltage changes from 5V to 2.5V.

Figure P3.6