Question

P.s last part with explanation be written explicitly if possible. Thx from now on

The question is mainly consisted from two sub-parts, respectively. A) (30 pts) According to the RS flip flop schematic given below, with using the outputs and clock signal, draw the probable Set (S) and Reset (R) input signals. с R s R o 10 B) (70 pts) An extremely popular version of an S-R flip flop can be called as J-K flip flop. The 2 parts of the version of R-S logic circuit is generally "Clock Pulse Detector” and “J-K flip flop logic circuit”. For this step, with only using the components given below: -XOR gate(s) -Not-inverter(s) -OR gate(s) J, K, C inputs BI) If the design procedure is plausible/possible, design a fundamental version of S-R flip flop with 3 inputs and 2 outputs. It is important that there are rules for this design procedure; • The number of components that you will use is up to you. You have to use at least one of the components given above (hint: There must be 3 inputs and 2 outputs in the logic circuit.) B2) If the design procedure is not possible, explain the situation in detail.

Answer 1

(A Q S RS Fif R Q S R C Q lo Thuth Table of SR flip flop. clock s R an/xiolo 4X107014 1 O ant) Qn Memory Gn. HOLD RESET State I → SET State: Invalid FORBIDDEN Stare 1 1 CS scanned with CamScanner

MS Flip-flop xo as of Do M ag Qin o 1 O CLK ra ff Aroid RAC SMS - on this master is applied with up clock and slave is applied with inverted clock, due to this. Master and slave will never change simultan simultaneously output changes only slave olf changes. when >gn this I bit, MiS to store is used fif - .. ICS

cerunt shown ib? Mis ff Qin Og. FF must have Q O o 0, IE edge togg I mis M.S.is level trigger L but act as edge trian using Differentratas. e CLK his without act as edge trigger ekt A U ☺ CLK > level trigges. OM act as up to Slave, ) os slave act ab. edge triggere 14.5 IS na level trigger s edge trigger > MS if is used in high speed digital ekt CS