7. Use a FSM to implement a counter with RESET function. The counter should meet the following requirements:
(1) The counter counts 0, 2, 1, 3, 0;
(2) The RESET is asynchronous, not synchronized with the CLOCK signal. If RESET signal is low, the counter resets to 0.
Please provide the state bubble diagram, state table, K-Maps, schematic for the counter.
Provided the d flip flopp IC 74LS74 as active low reset which is asynchronous in nature which meets our requirement of rest ( active low pin ) in the design
When Reset is low the d flip flop output will be set to "0" making both flip flops output Q1 = 0 , Q0 = "0" ;
Which makes current state S0 and output C1 , C0 = 00
Thus our requirement is achieved with the help of Reset present at the flip flop inputs in the FSM implementation
Digital circuit of counter
7. Use a FSM to implement a counter with RESET function. The counter should meet the...
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