Question

a. The diagram shows an 8-bit shifter that shifts its input one place to the left. Write a VHDL module for the shifter. B (7 down to 0) Lout A (7 down to 0

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity shift_register is
port (
Clk : in std_logic; -- clock input
A : in std_logic_vector(7 downto 0);
Rin : in std_logic;
B : out std_logic_vector(7 downto 0);
Iout : out std_logic
);
end shift_register;

architecture behavioral of shift_register is
begin

process(Clk)  
begin
if (Clk'event and Clk = '1') then
B <= A(6 downto 0) & Rin;
Iout <= A(7);
end if;
end process;

end behavioral;